PIC18F45J11-I/ML【PDF 19/228 页】IC PIC MCU FLASH 32K 2V 44-QFN

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2010 Microchip Technology Inc.

DS70138G-page 115

dsPIC30F3014/4013

Receive Error Interrupts:

A receive error interrupt is indicated by the ERRIF

bit. This bit shows that an error condition

occurred. The source of the error can be deter-

mined by checking the bits in the CAN Interrupt

- Invalid Message Received:

If any type of error occurred during reception of

the last message, an error is indicated by the

IVRIF bit.

- Receiver Overrun:

The RXnOVR bit indicates that an overrun

condition occurred.

- Receiver Warning:

The RXWAR bit indicates that the Receive Error

Counter (RERRCNT<7:0>) has reached the

warning limit of 96.

- Receiver Error Passive:

The RXEP bit indicates that the Receive Error

Counter has exceeded the error passive limit of

127 and the module has gone into error passive

state.

17.5

Message Transmission

17.5.1

TRANSMIT BUFFERS

The CAN module has three transmit buffers. Each of

the three buffers occupies 14 bytes of data. Eight of the

bytes are the maximum 8 bytes of the transmitted mes-

sage. Five bytes hold the standard and extended

identifiers and other message arbitration information.

17.5.2

TRANSMIT MESSAGE PRIORITY

Transmit priority is a prioritization within each node of

the pending transmittable messages. There are

4 levels

transmit

priority.

TXPRI<1:0>

(CiTXnCON<1:0>, where n = 0, 1 or 2, represents a

particular transmit buffer) for a particular message buf-

fer is set to ‘11’, that buffer has the highest priority. If

TXPRI<1:0> for a particular message buffer is set to

‘10’ or ‘01’, that buffer has an intermediate priority. If

TXPRI<1:0> for a particular message buffer is ‘00’, that

buffer has the lowest priority.

17.5.3

TRANSMISSION SEQUENCE

To initiate transmission of the message, the TXREQ bit

(CiTXnCON<3>) must be set. The CAN bus module

resolves any timing conflicts between setting of the

TXREQ bit and the Start-of-Frame (SOF), ensuring that if

the priority was changed, it is resolved correctly before the

SOF occurs. When TXREQ is set, the TXABT

(CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR

(CiTXnCON<4>) flag bits are automatically cleared.

Setting TXREQ bit simply flags a message buffer as

enqueued for transmission. When the module detects

an available bus, it begins transmitting the message

which has been determined to have the highest priority.

If the transmission completes successfully on the first

attempt, the TXREQ bit is cleared automatically and an

interrupt is generated if TX1IE was set.

If the message transmission fails, one of the error

condition flags is set, and the TXREQ bit remains set,

indicating that the message is still pending for transmis-

sion. If the message encountered an error condition

during the transmission attempt, the TXERR bit is set,

and the error condition may cause an interrupt. If the

message loses arbitration during the transmission

attempt, the TXLARB bit is set. No interrupt is

generated to signal the loss of arbitration.

17.5.4

ABORTING MESSAGE

TRANSMISSION

The system can also abort a message by clearing the

TXREQ bit associated with each message buffer.

Setting the ABAT bit (CiCTRL<12>) requests an abort

of all pending messages. If the message has not yet

started transmission, or if the message started but is

interrupted by loss of arbitration or an error, the abort is

processed. The abort is indicated when the module

sets the TXABT bit and the TXnIF flag is not

automatically set.

17.5.5

TRANSMISSION ERRORS

The CAN module detects the following transmission

errors:

Acknowledge error

Form error

Bit error

These transmission errors do not necessarily generate

an interrupt but are indicated by the transmission error

counter. However, each of these errors causes the

transmission error counter to be incremented by one.

Once the value of the error counter exceeds the value

of 96, the ERRIF (CiINTF<5>) and the TXWAR bit

(CiINTF<10>) are set. Once the value of the error

counter exceeds the value of 96, an interrupt is

generated and the TXWAR bit in the Error Flag register

is set.

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